포지션 상세
페블스퀘어는 PIM아키텍처를 기반으로 AI 반도체 설계와 AI 솔루션을 개발하는 팹리스 기업입니다. 폰 노이만(Von Neumann)구조의 한계를 극복하기 위해 고성능/초저전력의 PIM기반 AI 반도체를 성공적으로 양산하고, 멀티 코어 AI 반도체를 개발하여 국내외에서 실증 중이며 AI 반도체 상용화와 활용 촉진을 위해 다양한 AI 솔루션을 개발 중입니다.
• Integrate your IP into a bigger and more complex IP
• Support all front-end integration activities like Lint, CDC, Synthesis, and ECO
• Implement design automation via Python or other languages
• Work with other specialists that are members of the SOC Design, SOC Design Verification, Emulation, STA, and Physical Design teams
• Collaborate with software and systems teams to ensure a high-quality system
• Experience Required: 8+ years
• Expertise in RTL and/or testbench development using Verilog/SystemVerilog.
• Experience with digital ASIC/SOC design flow from RTL to silicon characterization.
• Ability to understand project specifications and come up with a comprehensive set of requirements and develop verification test-plans
• Experience debugging RTL designs using an HDL simulator
• Familiar with code base management method including subversion, git, GitHub, etc.
• Familiar with Synopsys and Cadence EDA tools for Simulation, Synthesis, Timing (STA), Formal and Assertion based verification, etc.
• Excellent communication skills both verbal and written for documentation and reporting
• Fluent English language
주요업무
• Design, implement, and debug complex logic designs• Integrate your IP into a bigger and more complex IP
• Support all front-end integration activities like Lint, CDC, Synthesis, and ECO
• Implement design automation via Python or other languages
• Work with other specialists that are members of the SOC Design, SOC Design Verification, Emulation, STA, and Physical Design teams
• Collaborate with software and systems teams to ensure a high-quality system
자격요건
• BS (or higher degree) in Electrical Engineering or related disciplines• Experience Required: 8+ years
• Expertise in RTL and/or testbench development using Verilog/SystemVerilog.
• Experience with digital ASIC/SOC design flow from RTL to silicon characterization.
• Ability to understand project specifications and come up with a comprehensive set of requirements and develop verification test-plans
• Experience debugging RTL designs using an HDL simulator
• Familiar with code base management method including subversion, git, GitHub, etc.
• Familiar with Synopsys and Cadence EDA tools for Simulation, Synthesis, Timing (STA), Formal and Assertion based verification, etc.
• Excellent communication skills both verbal and written for documentation and reporting
• Fluent English language
