포지션 상세
페블스퀘어는 PIM아키텍처를 기반으로 AI 반도체 설계와 AI 솔루션을 개발하는 팹리스 기업입니다. 폰 노이만(Von Neumann)구조의 한계를 극복하기 위해 고성능/초저전력의 PIM기반 AI 반도체를 성공적으로 양산하고, 멀티 코어 AI 반도체를 개발하여 국내외에서 실증 중이며 AI 반도체 상용화와 활용 촉진을 위해 다양한 AI 솔루션을 개발 중입니다.
• Perform layout verification like LVS/DRC/Antenna, quality check and documentation.
• Responsible for on-time delivery of block-level layouts with acceptable quality.
• Experience in analog/custom layout design in advanced CMOS process.
• Expertise in Cadence VLE/VXL and Calibre DRC/LVS is a must.
• Should have hands on experience of Critical Analog Layout design of blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc.,
• Good understanding of Analog Layout fundamentals (e.g. Matching, Electro-migration, Latch-up, coupling, cross-talk, IR-drop, active and passive parasitic devices etc.)
• Understanding layout effects on the circuit such as speed, capacitance, power, and area etc.,
• Ability to understand design constraints and implement high-quality layouts.
• Good command and problem-solving skills in over Physical layout verification.
• Multiple Tape out support experience will be an added advantage.
• Scripting and automation experience is good to have but not mandatory.
• Excellent communication skills both verbal and written for documentation and reporting
• Fluent English language
• BS (or higher degree) in Electrical Engineering or related disciplines
• Experience Required: 5+ Years
주요업무
• Responsible for Design and development of critical analog, mixed-signal, custom digital block, and full chip level integration support.• Perform layout verification like LVS/DRC/Antenna, quality check and documentation.
• Responsible for on-time delivery of block-level layouts with acceptable quality.
자격요건
• Experience in memory device layout of Nor flash, Nand flash, SRAM or DRAM• Experience in analog/custom layout design in advanced CMOS process.
• Expertise in Cadence VLE/VXL and Calibre DRC/LVS is a must.
• Should have hands on experience of Critical Analog Layout design of blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc.,
• Good understanding of Analog Layout fundamentals (e.g. Matching, Electro-migration, Latch-up, coupling, cross-talk, IR-drop, active and passive parasitic devices etc.)
• Understanding layout effects on the circuit such as speed, capacitance, power, and area etc.,
• Ability to understand design constraints and implement high-quality layouts.
• Good command and problem-solving skills in over Physical layout verification.
• Multiple Tape out support experience will be an added advantage.
• Scripting and automation experience is good to have but not mandatory.
• Excellent communication skills both verbal and written for documentation and reporting
• Fluent English language
• BS (or higher degree) in Electrical Engineering or related disciplines
• Experience Required: 5+ Years
