포지션 상세
We are building Terafab, a vertically integrated semiconductor factory at an unprecedented scale. The facility houses logic, memory, packaging, test, and lithography mask production under one roof, optimized for rapid iteration and maximum compute density per square foot. Process engineering is where Terafab technology gets built, atom by atom, and lithography will define the limit of what we can build. You will develop and own patterning processes across three distinct chip families: edge-inference processors, space-hardened chips for orbital satellites, and high-bandwidth memory.
• Qualify scanners (EUV and DUV) from installation through production readiness, including dose-focus matrices, CDU, and overlay
• Own in-house mask shop process development (resist, etch, inspection, repair) and co-optimize reticle-scanner strategies using tight feedback loops
• Establish overlay and registration control strategies, scanner-to-scanner matching, and APC loop integration
• Analyze processes from a first-principles, physics-based approach to understand and manipulate mechanisms, not just recipes
• Lead root cause analysis, establish inline metrology and SPC control strategies, and drive systematic yield improvement
• Support 24/7 manufacturing operations through rotations, on-call availability, and rapid response to critical production issues
• Drive next-generation lithography materials and process development
• 5+ years of hands-on lithography process engineering experience in a semiconductor fab, especially ＜7nm in a logic, memory, or foundry environment
• Deep experience with scanner qualification (ASML or equivalent), resist process development, and process of record (POR) establishment at advanced nodes
• Proficiency with lithography metrology tools: CD-SEM, OCD, overlay metrology, defect inspection, and resist profile characterization
• Strong DOE skills and statistical analysis capability (JMP, Python, or R)
• Ability to work closely and proactively across lithography, etch, thin films, integration, and equipment engineering teams
주요업무
• Develop and qualify EUV and ArFi resist processes, exposure parameters, and coat/develop optimization for critical layers• Qualify scanners (EUV and DUV) from installation through production readiness, including dose-focus matrices, CDU, and overlay
• Own in-house mask shop process development (resist, etch, inspection, repair) and co-optimize reticle-scanner strategies using tight feedback loops
• Establish overlay and registration control strategies, scanner-to-scanner matching, and APC loop integration
• Analyze processes from a first-principles, physics-based approach to understand and manipulate mechanisms, not just recipes
• Lead root cause analysis, establish inline metrology and SPC control strategies, and drive systematic yield improvement
• Support 24/7 manufacturing operations through rotations, on-call availability, and rapid response to critical production issues
• Drive next-generation lithography materials and process development
자격요건
• BS or MS in chemical engineering, materials science, electrical engineering, physics, or related technical field• 5+ years of hands-on lithography process engineering experience in a semiconductor fab, especially ＜7nm in a logic, memory, or foundry environment
• Deep experience with scanner qualification (ASML or equivalent), resist process development, and process of record (POR) establishment at advanced nodes
• Proficiency with lithography metrology tools: CD-SEM, OCD, overlay metrology, defect inspection, and resist profile characterization
• Strong DOE skills and statistical analysis capability (JMP, Python, or R)
• Ability to work closely and proactively across lithography, etch, thin films, integration, and equipment engineering teams
