테슬라(Tesla)-Sr. Yield and Metrology Engineer
테슬라(Tesla)-Sr. Yield and Metrology Engineer
테슬라(Tesla)-Sr. Yield and Metrology Engineer
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테슬라(Tesla)서울 강남구경력 5년 이상

Sr. Yield and Metrology Engineer

포지션 상세

We are building Terafab, a vertically integrated semiconductor factory at an unprecedented scale. The facility houses logic, memory, packaging, test, and lithography mask production under one roof, optimized for rapid iteration and maximum compute density per square foot. Yield is the ultimate scorecard of a fab. As a Yield & Metrology Engineer at Terafab, you will build the data infrastructure, defect learning systems, and metrology strategy that drives Terafab chip manufacturing to world-class yield levels.

주요업무

• Build Terafab's yield learning infrastructure from the ground up: defect inspection sampling plans, inline metrology flows, and electrical test correlation frameworks
• Lead systematic yield analysis using defect pareto, binning analysis, parametric correlation, and spatial signature decomposition
• Own the inline metrology strategy across all critical layers: CD, overlay, film thickness, defect density, and electrical continuity
• Drive defect reduction programs across all yield-limiting defect types such as particles, pattern defects, etch residues, shorts, and opens
• Partner with process, equipment, and integration engineers to close the loop between yield data and corrective actions
• Develop automated data pipelines, yield dashboards, and early warning systems using Python, SQL, and internal data tooling
• Lead physical failure analysis (PFA) including FIB/SEM cross-sections, EBAC, and TEM sample preparation
• Build die-level yield models and simulation capabilities to project yield at scale and prioritize defect investment

자격요건

• BS in electrical engineering, physics, materials science, or equivalent experience
• 5+ years of yield engineering or metrology engineering experience in a leading-edge semiconductor fab
• Strong proficiency in yield analysis: defect pareto, spatial analysis, electrical bin correlation, and parametric yield modeling
• Experience with defect inspection and review tools (KLA, Camtek) and defect classification systems
• Experience building yield learning systems from scratch in a greenfield fab environment
• Experience in ML/AI-based defect classification or yield prediction modeling
• Solid programming skills in Python or R for data analysis, visualization, and process control automation
• Familiarity with wafer sort, electrical test structures, and EDS analysis for yield learning
• Familiarity with FIB/SEM sample preparation and advanced PFA techniques

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서울특별시 강남구 테헤란로 419, 9층
본 채용정보는 원티드랩의 동의없이 무단전재, 재배포, 재가공할 수 없으며, 구직활동 이외의 용도로 사용할 수 없습니다.
본 채용 정보는 에서 제공한 자료를 바탕으로 원티드랩에서 표현을 수정하고 이의 배열 및 구성을 편집하여 완성한 원티드랩의 저작자산이자 영업자산입니다. 본 정보 및 데이터베이스의 일부 내지는 전부에 대하여 원티드랩의 동의 없이 무단전재 또는 재배포, 재가공 및 크롤링할 수 없으며, 게재된 채용기업의 정보는 구직자의 구직활동 이외의 용도로 사용될 수 없습니다. 원티드랩은 에서 게재한 자료에 대한 오류나 그 밖에 원티드랩이 가공하지 않은 정보의 내용상 문제에 대하여 어떠한 보장도 하지 않으며, 사용자가 이를 신뢰하여 취한 조치에 대해 책임을 지지 않습니다.
<저작권자 (주)원티드랩. 무단전재-재배포금지>